1. Field of the Invention
The present invention relates to a capacitor, and more particularly to a capacitor in which the lower electrode and an interconnect line are located at the same level.
2. Description of the Prior Art
Capacitors are integrated in various integrated circuits. For example, capacitors can be used as decoupling capacitors to provide improved voltage regulation and noise immunity for power distribution. Capacitors also have wide applications in analog/logic, analog-to-digital, mixed signal, radio frequency circuits and so on.
Refer to FIGS. 1a to 1f, which are cross-sectional views illustrating the process flow of fabricating a metal capacitor in an intermetal dielectric layer according to conventional process. Referring to FIG. 1a, a semiconductor substrate 100 including a MOS transistor (not shown) is provided. A plurality of first level metal lines 120 and 121 are formed on the substrate 100, and a first intermetal dielectric layer 110 is formed on the substrate 100 and the metal lines 120 and 121. A first resist pattern 140 is formed on the first intermetal dielectric layer 110. The first intermetal dielectric layer 110 is then patterned by photolithography and etching using the first resist pattern 140 as a mask to form a via hole. Metal is then filled into the via hole to form a first plug 150, and the first resist layer 140 is removed.
Next, referring to FIG. 1b, a metal layer 160, an insulating layer 170, and a metal layer 180 are successively formed on the entire surface of the first intermetal dielectric layer 110 and the first plug 150. A second resist pattern 190 is formed on the metal layer 180. The second resist pattern 190 defines a region for forming a metal capacitor in the future, which is called a capacitor region 130. Then, the metal layer 160, the insulating layer 170, and the metal layer 180 are patterned by photolithography and etching using the second resist pattern 190 as a mask to define a metal capacitor 200 which includes a lower electrode 160xe2x80x2, an insulating layer 170xe2x80x2, and an upper electrode 180xe2x80x2 as shown in FIG. 1c. 
Next, referring to FIG. 1d, a second intermetal dielectric layer 210 is formed on the metal capacitor 200 and the first intermetal dielectric layer 110.
Next, referring to FIG. 1e, a third resist pattern 220 is formed on the second intermetal dielectric layer 210. The second intermetal dielectric layer 210 is then patterned by photolithography and etching by using the third resist pattern 220 as a mask to form a via hole in the capacitor region 130 reaching the upper electrode 180xe2x80x2 and a via hole reaching first level metal line 120, which are then filled with metal to form a second plug 230 and a third plug 240.
Finally, referring to FIG. 1f, second level metal lines 250 and 251 are formed on the plugs 230 and 240 respectively for electrical connection.
The conventional method for fabricating a metal capacitor in an intermetal dielectric layer has the following disadvantages:
(1) Two masks are needed to fabricate a metal capacitor. That is to say, one mask is needed when the plug 150 is defined and the other mask is needed when the metal capacitor is patterned. Thus, costs are high.
(2) Since the cross-sectional area of the plug 150 is small, when the plug 150 is defined, etching is very difficult to control, complicating the process.
(3) When the plugs 230 and 240 are concurrently defined, since the etching heights for the two plugs differ a lot, etching is difficult to conduct, complicating the process.
(4) Since the metal layer 160, the insulating layer 170, and the metal layer 180 for forming the metal capacitor are formed on the entire surface, production costs are very high.
(5) When the metal layer 160, the insulating layer 170, and the metal layer 180 are etched to form the metal capacitor, it is very easy to cause damage on the edge portion of the metal capacitor. Thus, yield is decreased.
The object of the present invention is to solve the above-mentioned problems and to provide a capacitor in which the lower electrode and an interconnect line are located at the same level. The lower electrode and the interconnect line can be in-situ (concurrently) formed. Thus, one mask can be omitted compared with the conventional method, and production costs can be reduced.
To achieve the above-mentioned object, the capacitor of the present invention includes a first conductive line and a second conductive line on a substrate located at the same level, wherein the second conductive line defines a capacitor region and is used as a lower electrode of the capacitor; an insulating layer on the substrate, the first conductive line, and the second conductive line; and a third conductive line on the insulating layer in the capacitor region such that the third conductive line is used as an upper electrode of the capacitor.
Above the upper electrode of the capacitor, the capacitor of the present invention can further includes a dielectric layer on the upper electrode and the insulating layer, wherein the dielectric layer has a first via hole reaching the first conductive line and a second via hole reaching the upper electrode; a first metal plug filled in the first via hole; a second metal plug filled in the second via hole; a fourth conductive line on the first plug; and a fifth conductive line on the second plug, wherein the fourth and the fifth conductive lines are located at the same level.
The main difference between the capacitor of the present invention and conventional one resides in the fact that, in the present invention, the lower electrode and an interconnect line are located at the same level. That is to say, the lower electrode and the interconnect line can be in-situ (concurrently) formed. Thus, one mask can be omitted compared with the conventional capacitor, and a step of photolithography and etching can be omitted.
In the present invention, production costs are decreased, process complexity is decreased, yield is enhanced, and the object of minaturizing integrated circuits is achieved.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and of the scope of the invention will become apparent to those skilled in the art from this detailed description.